Infineon Technologies: New Power MOSFET OptiMOS ™ Enables Innovative Source-Down Technology for PQFN 3.3 x 3.3 mm2 in 25 V to 100 V variants

Munich, Germany – January 7, 2022 – High power density, optimized performance and ease of use are key requirements when designing modern electrical systems. To offer practical solutions to design challenges in end-use applications, Infineon Technologies AG (FSE: IFX / OTCQX: IFNNY) is launching the next generation of OptiMOS â„¢ Source-Down (SD) power MOSFETs. They come in a 3.3 x 3.3mm PQFN 2 housing and a wide voltage class ranging from 25 V to 100 V. This housing sets a new standard in power MOSFET performance, offering higher efficiency, higher power density, superior thermal management and low nomenclature. The PQFN processes requests, including motor drives, SMPS for server and telecom and OR-ing, as well as battery management systems.

Compared to the standard Drain-Down concept, the latest Source-Down housing technology allows for a larger silicon matrix in the same housing outline. In addition, the losses provided by the housing, limiting the overall performance of the device, can be reduced. This allows a reduction of R DS (activated) up to 30 percent over the industry-leading Drain-Down package. The system benefit is a reduced form factor with the option to upgrade from a 5 x 6mm SuperSO8 2 impression at a 3.3 x 3.3 mm PQFN 2 package with a space reduction of about 65 percent. This makes more efficient use of the available space, improving power density and system efficiency in the final system.

Additionally, in the Source-Down concept, heat is dissipated directly into the PCB via a thermal pad rather than the lead wire or copper clamp. This improves thermal resistance R thJC of more than 20%, from 1.8 K / W to 1.4 K / W, thus allowing a simplified thermal management. Infineon offers two different footprint versions and layout options: SD Standard-Gate and SD Center-Gate. The Standard-Gate layout simplifies the instant replacement of drain-down packages, while the Center-Gate layout allows for optimized and easier parallelization. These two options can provide optimal arrangement of peripherals in the PCB, optimized PCB noise and ease of use.


OptiMOS â„¢ Source-Down Power MOSFETs Now Available in 3.3 x 3.3mm PQFN 2 packaging, a wide range of voltage classes from 25 to 100 V, and two different fingerprint versions. More information is available at

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